Interview Questions for Design Verification Engineer

Interviewer can ask questions from different topics. These are mainly

1. Prior project experience
2. Logic implementation
3. Constraint randomization
4. Bit manipulation
5. UVM and class-related
6. Verilog design basic (fundamental)
7. Verification Stretegies
8. Assertion
9. Coverage

First Technical Discussion Questions:

1. Tell me about yourself, who was the client, with your experience in your projects.
2. What are the design bugs you find?
3. What was the role and responsibility in your projects?
4. What types of assertions you have written?
5. What is the driver and sequencer handshaking mechanism?
6. How will you make or gate with 2:1 mux?
7. If you have given the full adder as dut, what are the features and how you would verify it?
8. Give me 3 input conditions on which the whole full adder can verify.
9. Write a constraint to generate the random, ascending dynamic array.
10. What is raise objection and drop objections?
11. How many uvm phases are there in uvm?
12. What speeds do you run the Ral model?

Second Technical Discussion Questions:

1. Tell me about yourself.
2. How would you write the scoreboard of ddr4 memory?
3. How would you generate the 10101010 pattern using constraints?
4. From the code, I need to find the code output from the display?
5. What is inheritance?
6. What is polymorphism?
7. How do the driver and sequencer communications happen?
8. What is the use of a virtual sequencer?
9. What is the use of virtual sequence?
10. What is the difference between config_db and resource_db?
11. Let’s say there are 4 processes. The second process starts when the first process is completed. The third and fourth processes should start when both the first and second sequences stop. How would write the code?
12. How would write the constraint that the signal boundary should not be greater than 4k?
13. Let’s say in memory, There is a bug like when we read from the 0 location it gives the data of 1 location. And vice versa.
14. How many bins will be created in a={1,2,3,4} and b[]={1,2,3,4}
15. What does it mean if functional coverage is 100% and code coverage is 50%.?
16. Do you have any questions to ask?