Table of Contents: System Verilog

  • Overview of System Verilog
  • System Verilog Datatypes
    • What are Data types and describe their types of them?
    • Difference between signed and unsigned data types?
    • Difference between two-state and four-state data types?
    • List of two-state data types
    • List of four-state data types
    • What is string data type?
    • What are Enum data types?
  • List of Operators
  • Flow Control Constructs
  • Communication Constructs
  • OOPs concepts
    • What is the class like?
    • How can we create a handle and object of class?
    • What is a constructor in a class?
    • What is “this” construct?
    • What is the benefit of using “super”?
    • What is an “extern” construct?
    • Abstraction
    • Polymorphism
    • Inheritance
    • encapsulation
    • Virtual methods
    • Abstract Class or Pure virtual methods
    • Use of “typedef” construct and its uses
    • Randomization of data objects
    • What is a shallow copy?
    • What is a deep copy?
    • Static properties/methods
    • What is the scope resolution Operator in the system Verilog?
    • Constant class Property
    • Parameterized Class
  • Randomization
    • What is randomization in System Verilog?
    • Difference between “$random” and “$u_random” constructs
    • What is the difference between “rand” and “randc” constructs?
  • Constraints
  • Interface Construct
  • MISC constructs
  • Coverage
  • Assertions
  • Full Testbench Example
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