System Verilog data types

Here we will discuss commonly used different System Verilog data types. This is a starting topic for every beginner so it is important to understand. We will understand this topic in detail.

What is Data type and describe different types of System Verilog Datatypes?

A data type is nothing but representing a variable’s value. We need many types of data for generating test bench packets, and also making test benches.

Data types used in Verilog

Verilog has two basic data types reg and wire which are used to store variables and drive the signals respectively. These data types hold four state values which are 0, 1, Z, X. Reg/wire has possible values as below.

Values data type holdStates of signal
0Low level
1High level
XImpedance
ZOpen terminal

Commonly used System Verilog data types

System Verilog has added many new data types for both design and verification.

Data typeHoldSizeSyntaxUsed for
Bit0/11bit ato represent a single binary value
Reg0/1/x/z1reg ato represent a register, that stores data
Wire0/1/x/z1wire adouble-precision floating-point values
Logic0, 1, X (unknown), and Z (high impedance)1logic acan drive or store values.
IntegerSigned or unsigned integer values32integer ato represent signed or unsigned whole numbers
Realdouble-precision floating point values64real ato represent real numbers with decimal points
ByteUnsigned byte values8byte ato represent a sequence of eight bits.
ShortintSigned short integer values16shortint aUsed for real-time quad-precision floating point
IntSigned integer32Int aUsed for Signed integer
LongintSigned long integer64longint aUsed for Signed long integer
TimeUnsigned simulation time64time aUsed for Unsigned simulation time
Realtimequad-precision floating point128realtime aUsed for signed short integer values
Shortrealsingle-precision floating point32shortreal aUsed for

In addition to these basic data types, System Verilog also supports arrays, queues, and dynamic arrays, allowing you to work with multiple values of the same type simultaneously. You can also create your own custom data types using structures, unions, and typedefs.

What is the difference between signed and unsigned data types?

Data TypeDescription
bitUnsigned single bit
logicUnsigned multi-bit
byteUnsigned byte
shortintSigned short integer
intSigned integer
longintSigned long integer
integerSigned or unsigned integer
timeUnsigned simulation time
shortrealsingle-precision floating point
realdouble-precision floating point
realtimequad-precision floating point

What is the difference between two-state and four-state data types?

The two-state data types are those that can have a value of only 0 or 1 where as the four-state data types can have values 0(Logic Low), 1(Logic High), z(Open terminal), and X(High Impedance).

What is logic data type? Where can we use it?

It is an improved version of reg data types where continuous assignments, gates and modules can drive it. However, it can use to store variables. But it cannot be driven by multiple drivers while modelling a bidirectional bus.  

Why are two state data types added in System Verilog?

The two-state data types are used for better test bench performance of test benches and reduced memory usage.

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