Verilog Interview Questions (Basic Level)

1. What is Verilog?
2. Is it a RTL design language or verification language?
3. What other design languages are you familiar with?
4. What is module in Verilog explain in detail?
5. What is difference between unary, binary and ternary Operators?
6. What are X and Z values in Verilog?

Please note that We are still updating the pages, you might see different set of questions in future.